The entire disclosure including the specifications, claims, drawings, and abstracts of Japanese patent applications Nos. Hei 9-313359, filed on Nov. 14, 1997 and Hei 9-313360, filed on Nov. 14, 1997 is incorporated herein by reference.
This invention relates to non-volatile semiconductor memory using ferroelectric capacitors, and more specifically to a semiconductor memory comprising ferroelectric memory FETs each having at least a ferroelectric layer between a gate electrode and a semiconductor layer, and to a method of gaining access to the semiconductor memory.
A ferroelectric memory has for example an FET structure as shown in FIG. 14 in which a ferroelectric layer 54 and a gate electrode 55 are provided on part of a semiconductor substrate 51 between a drain region 52 and a source region 53 formed on a semiconductor substrate 51. It is known that; when a high voltage is applied between the gate electrode 55 and the semiconductor substrate 51, polarization charge is produced, and xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is written depending on the direction of polarization; the data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d can be read by applying a low voltage to the gate electrode; and the data do not disappear even if power is turned off. Therefore it is known that the device can be used as a non-volatile memory of non-destructive reading type. However, practical use of a memory is yet to be realized in which the above-described memory cells are arranged as a matrix circuit. That is, a method is known in which each of cells arranged as a matrix may be accessed through selection elements provided, two for each cell, one for writing and the other for reading. However, when two selection elements are used for each cell respectively, a problem arises that the cell area increases and the degree of integration extremely decreases.
On the other hand, an access method is considered for example for a memory made of matrix-arranged ferroelectric capacitors, in which a power source voltage Vcc is equally divided into three and applied to each line, in order to prevent a voltage from being applied to a cell other than an intended, selected cell at the time of writing for example and prevent the data from being rewritten. To apply the three equally divided voltage application method to a memory in which ferroelectric memory FETs are arranged as a matrix, the following access method may be considered.
That is, as shown in the simplified drawing FIG. 13(a), in the case cells comprising a plurality of ferroelectric memory FETs in matrix-pattern are wired and xe2x80x9c1xe2x80x9d is to be written to a selected cell P, the writing is carried out by applying Vcc to a word line WL1 on which the selected cell P is present, ⅓ of Vcc to a word line WL2 on which the selected cell P is absent, 0 to a bit line BL1 on which the selected cell P is present, and ⅔xc2x7Vcc to a bit line BL2 on which the selected cell P is absent. In the case xe2x80x9c0xe2x80x9d is to be written to the selected cell P, 0 is applied to the word line WL1, ⅔ of Vcc to the word line WL2, Vcc to the bit line BL1, and ⅓ of Vcc to the bit line BL2. When the selected cell P is to be read, V1 (a voltage lower than Vcc at the time of reading) is applied to the word line WL1, 0 to the word line WL2, 0 to the bit line BL1, and VSA (data detecting voltage) to a data line DL1. The sequence in writing and reading xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d is shown in FIG. 13(b). The blank boxes in FIG. 13(b) denote that the corresponding lines are open or at 0 V. As a result, when the writing is carried out, a high voltage of Vcc or xe2x88x92Vcc is applied between the gate electrode and the semiconductor substrate to write xe2x80x9c1xe2x80x9d or xe2x80x9c0.xe2x80x9d At this time, the voltage applied to a cell not selected is ⅓ of Vcc or xe2x88x92⅓ of Vcc and writing is not carried out. At the time of reading, while V1 is applied between the gate electrode and the semiconductor substrate in selected cells, cells not selected are open or at 0 V, almost no voltage is applied, and no reading is carried out.
While writing and reading can be made by selecting only an intended cell as described above, at the time of writing for example, the voltage of ⅓ of Vcc is also applied to cells not selected. When the voltage ⅓ of Vcc is applied, polarization of ferroelectric capacitor (polarization corresponding to the stored data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) is disturbed. After repeated applications, there is a concern that the data stored in cells to which no writing is made may change. Under such a circumstance, there are following problems: For the small-sized semiconductor memories using the ferroelectric memory cells, an access method without disturbing the data stored in the memory cells not selected is yet to be established. And as described above, a semiconductor memory has not yet been put to practical use in which the ferroelectric memory FETs are arranged as a matrix of cells.
An object of this invention made to solve the above-described problems is to provide a method of writing and reading with a semiconductor memory constituted with ferroelectric memory FETs arranged as a matrix, allowing to write and/or read data to and from only a selected memory cell without the data being destroyed by a disturbing voltage applied to cells not selected without providing each cell with a selection element.
Another object of the invention is to provide a semiconductor memory having ferroelectric memory FETs constituted to be reliably used by restoring the data even when the data are disturbed and deteriorated as a result of applying a low voltage to cells not selected as described above.
Still another object of the invention is to provide an access method with a semiconductor memory constituted with ferroelectric memory FETs arranged as a matrix, allowing to prevent stored data from being disturbed even with an access method in which a power source voltage is equally divided into three and applied.
That is to say, the object of the invention is providing a semiconductor memory, etc. using ferroelectric memory with which stored data are not disturbed.
According to the invention, a method of writing data to a semiconductor memory including a memory cell which comprises ferroelectric memory FETs each having a ferroelectric layer disposed between a gate electrode and a semiconductor layer is characterized in that a writing voltage is applied after applying a voltage that is opposite in direction to the writing voltage.
According to the invention, a method of reading data from a semiconductor memory including a memory cell which comprises ferroelectric memory FETs each having a ferroelectric layer disposed on gate electrode side is characterized in that a reading voltage is applied after applying a voltage that is opposite in direction to the reading voltage.
The term ferroelectric memory FET having a ferroelectric layer between a gate electrode and a semiconductor layer refers to any memory element of an FET structure with at least a ferroelectric layer disposed between a gate electrode and a semiconductor layer, such as a structure (MFS structure) of a gate electrode (metal M)xe2x80x94ferroelectric (F)xe2x80x94semiconductor (S); a structure in which at least one layer other than ferroelectric layer is disposed between the metal M and a semiconductor S of the MFS structure; and a structure (MFMIS structure) of a gate electrode (M)xe2x80x94ferroelectric (F)xe2x80x94floating gate (M)xe2x80x94insulation film (I)xe2x80x94semiconductor (S).
When the above-described method is used, even if the disturbing voltage of ⅓ of Vcc is applied to cells not selected in the access method of equally dividing the power source voltage into three and applying to respective lines, the decrease in charge due to the disturbing voltage is restored by the constant application of a voltage in the opposite direction to that of the disturbing voltage in succession, and the data are prevented from being removed.
The voltage application to each memory cell at the time of writing can be made such that for example the power source voltage is equally divided into three and applied to each line. In that case, it is possible to apply the power source voltage to a selected cell while applying xc2x1⅓ of the power source voltage to cells not selected.
The above-mentioned memory can be constituted such that the memory cells made of the ferroelectric memory FETs are arranged as a matrix, gates of cells in a row in one direction are connected to form a word line, sources of cells in a row in one direction are connected to form a source line, drains of cells in a row in the other direction are connected to form a data line, and semiconductor layers of cells in a row in the other direction are connected to form a bit line. Writing and reading can be made by applying a voltage between the word line and the bit line.
The semiconductor memory using the ferroelectric layer of the invention comprises memory cells made of ferroelectric memory FETs each having a ferroelectric layer between a gate electrode and a semiconductor layer, buffer cells capable of transferring data from the memory cells, and buffer circuits that transfer data from a memory cell to a buffer cell and write the transferred data again to the memory cell.
This constitution allows to periodically refreshing data in the memory cell by the use of the buffer cell, so that the data are retained and prevented from disappearing over a long period of time.
This arrangement in which the memory cells are disposed as a matrix, the buffer cell comprises a row of cells capable of transferring data of at least one line of memory cells of lateral or vertical row of the memory cell, and the buffer circuit is capable of collectively transferring data of at least one line of the memory cell and also capable of writing again, allows it possible to transfer and write again data of every line at a time, so that data are refreshed within a short period of time.
If the buffer cell is made of a ferroelectric memory FET having a ferroelectric layer between a gate electrode and a semiconductor layer, dummy memory cells can be manufactured with the same process as that for the memory cells.
When the buffer circuit is constituted with a first selection element connected between the gate electrode of the buffer cell and the data line of the memory cell to control the transfer of the memory cell, a second selection element to read data from the buffer cell connected to the gate electrode of the buffer cell, and a transformer which transforms the voltage of the data read from the buffer cell and is connected to the bit line interconnecting the substrates of the memory cells, data can be refreshed any time by the control of the selection elements.
An access method for a semiconductor memory comprising memory cells made of ferroelectric memory FETs each having a ferroelectric layer between a gate electrode and a semiconductor layer, and buffer cells capable of transferring data of the memory cells is characterized in that the data of the memory cells are once transferred to the buffer cells and the transferred data are written again to the memory cells, so that the data of the memory cell are refreshed.
The refreshment of the data stored in the memory cells is preferably carried out either at constant time intervals depending on the disturbance characteristic obtained in advance for the data of the ferroelectric layer used in the memory cell or every time the number of writings and/or readings data to and from the memory cell reaches a predetermined value. In this case, the number of accesses, or the number of readings and writings may be counted with a counter, so that the data are refreshed when the number reaches a predetermined value.